The present invention relates generally to semiconductor memory devices and more particularly to memory structures and methods for forming a local interconnect layer within a conductive plate of a ferroelectric capacitor in a ferroelectric memory device.
In semiconductor memory devices, data is read from or written to the memory using address signals and various other control signals. In a random access memory (xe2x80x9cRAMxe2x80x9d), an individual binary data state (e.g., a bit) is stored in a volatile memory cell, wherein a number of such cells are grouped together into arrays of columns and rows accessible in random fashion along bitlines and wordlines, respectively, wherein each cell is associated with a unique wordline and bitline pair. Address decoder control circuits identify one or more cells to be accessed in a particular memory operation for reading or writing, wherein the memory cells are typically accessed in groups of bytes or words (e.g., generally a multiple of 8 cells arranged along a common wordline). Thus, by specifying an address, a RAM is able to access a single byte or word in an array of many cells, so as to read or write data from or into that addressed memory cell group.
Two major classes of random access memories include xe2x80x9cdynamicxe2x80x9d (e.g., DRAMs) and xe2x80x9cstaticxe2x80x9d (e.g., SRAMs) devices. For a DRAM device, data is stored in a capacitor, where an access transistor gated by a wordline selectively couples the capacitor to a bit line. DRAMs are relatively simple, and typically occupy less area than SRAMs. However, DRAMs require periodic refreshing of the stored data, because the charge stored in the cell capacitors tends to dissipate. Accordingly DRAMs need to be refreshed periodically in order to preserve the content of the memory. SRAM devices, on the other hand, do not need to be refreshed. SRAM cells typically include several transistors configured as a flip-flop having two stable states, representative of two binary data states. Since the SRAM cells include several transistors, however, SRAM cells occupy more area than do DRAM cells. However, SRAM cells operate relatively quickly and do not require refreshing and the associated logic circuitry for refresh operations.
A major disadvantage of SRAM and DRAM devices is volatility, wherein removing power from such devices causes the data stored therein to be lost. For instance, the charge stored in DRAM cell capacitors dissipates after power has been removed, and the voltage used to preserve the flip-flop data states in SRAM cells drops to zero, by which the flip-flop loses its data. Accordingly, SRAMs and DRAMs are commonly referred to as xe2x80x9cvolatilexe2x80x9d memory devices. Non-volatile (NV) memories are available, such as Flash and EEPROM. However, these types of non-volatile memory have operational limitations on the number of write cycles. For instance, Flash memory devices generally have life spans from 100K to 10MEG write operations.
Recently however, non-volatile ferroelectric RAM devices have been developed, which are commonly referred to as FERAMs or FRAMs. FERAM cells employ ferroelectric capacitors (FECaps) including a pair of capacitor plates with a ferroelectric material, such as SBT or PZT, as the capacitor dielectric situated between them. Ferroelectric materials have two different stable polarization states that may be used to store binary information, where the ferroelectric behavior follows a hysteresis curve of polarization versus applied voltage. FERAM memory cells are non-volatile memory devices, because the polarization state of an FECap remains when power is removed from the device.
Two types of memory cells are used commonly, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (referred to as a 1T/1C or 1C memory cell) requires less silicon area (thereby increasing the potential density of the memory array), but is less immune to noise, process and cycling variations. Additionally, a 1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C or 2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2C memory cell generally is more stable than a 1C memory cell.
As illustrated in prior art FIG. 1, a 1T/1C FeRAM cell 10 includes one transistor 12 and one ferroelectric storage capacitor 14. A bottom electrode of the storage capacitor 14 is connected to a drain terminal 15 of the transistor 12. The 1T/1C cell 10 is read from by applying a signal to the gate 16 of the transistor (word line WL)(e.g., the Y signal), thereby connecting the bottom electrode of the capacitor 14 to the source of the transistor (the bit line BL) 18. A pulse signal is then applied to the top electrode contact (the drive line DL or plate line PL) 19. The potential on the bit line 18 of the transistor 12 is, therefore, the capacitor charge divided by the bit line capacitance. Since the capacitor charge is dependent upon the bi-stable polarization state of the ferroelectric material, the bit line potential can have two distinct values. A sense amplifier (not shown) is connected to the bit line 18 and detects the voltage associated with a logic value of either 1 or 0. Frequently, the sense amplifier reference voltage is provided by a xe2x80x9creference cellxe2x80x9d, which comprises a ferroelectric or non-ferroelectric capacitor connected to another bit line that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of the shown ferroelectric memory cell is that a read operation is destructive. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. Since the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. One difference from a DRAM is that a ferroelectric memory cell will retain its state until it is interrogated, thereby eliminating the need of refresh.
As illustrated, for example, in prior art FIG. 2, a 2T/2C memory cell 20 in a memory array couples to a bit line 22 and an inverse of the bit line (xe2x80x9cbit line-barxe2x80x9d) 24 that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors 26 and 28 and two ferroelectric capacitors 30 and 32, respectively. The first transistor 26 couples between the bit line 22 and a first capacitor 30, and the second transistor 28 couples between the bit line-bar 24 and the second capacitor 32. The first and second capacitors 30 and 32 have a common terminal or plate line PL 34 to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors 26 and 28 of the dual capacitor ferroelectric memory cell 20 are enabled (e.g., via their respective word line WL 36) to couple the capacitors 30 and 32 to the complementary logic levels on the bit line 22 and the bar-bar line 24 corresponding to a logic state to be stored in memory. The common terminal 34 of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell 20 to one of the two logic states.
In a read operation, the first and second transistors 26 and 28 of the dual capacitor memory cell 20 are enabled via the word line 36 to couple the information stored on the first and second capacitors 30 and 32 to the bit line 22 and the bit line-bar line 24, respectively. A differential signal (not shown) is thus generated across the bit line 22 and the bit line-bar line 24 by the dual capacitor memory cell 20. The differential signal is sensed by a sense amplifier (not shown) that provides a signal corresponding to the logic level stored in memory.
Ferroelectric memory cells employing these FECaps provide certain performance advantages over other forms of non-volatile data storage devices, such as Flash and EEPROM type memories. For example, ferroelectric memories offer short programming (e.g., write access) times and low power consumption and lower voltage operation.
Several additional memory devices have been developed utilizing FECaps, such as the four transistor (4T) two capacitor (2C) non-volatile (NV) SRAM cell (4T/2C NV SRAM), and the FECap based reference cell noted above. In these NV FERAM devices, the FECap is commonly coupled to several (e.g., 3-5) MOS transistors or other such memory circuit elements through contacts and vias to the metal layer (e.g., M1) for interconnection. However, as device densities and memory speed requirements continue to increase, the M1 metal layer tends to become increasing crowded and may limit the layout area available, particularly for the memory cells. In addition, the area and length required by the interconnection contacts and vias coupling the circuit elements to the M1 layer, further limits the layout area, the size of the FECaps, and the minimum resistance between the interconnected circuit elements. Accordingly, there is a need for an improved memory structure for interconnecting a non-volatile ferroelectric capacitor with associated circuit elements in a ferroelectric device.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention relates to an improved ferroelectric device structure and methods for forming a local interconnect layer with a conductive plate of a ferroelectric capacitor in a ferroelectric device. The device comprises a ferroelectric capacitor and a plurality of circuit elements, which are locally interconnected using the metal or otherwise conductive layer formed from one of the conductive plates of the ferroelectric capacitor. In various ferroelectric circuits that use an FECap, the FECap is required to electrically couple to several MOS transistors or other such circuit elements. Typically, this interconnection is done by routing through a contact and/or via from the FECap down to the circuit element in an active region, then back up through the M1 layer interconnect layer, then finally back down again to multiple circuit elements thru respective contacts and/or vias associated with respective circuit elements. This extensive use of the M1 tends to crowd the M1 and may limit layout density.
By contrast, the present invention uses a plate of the ferroelectric capacitor as a local interconnection layer for multiple circuit elements, rather than using the M1. Although the invention is described and illustrated in exemplary circuits and structures using the bottom electrode of the FECap, it is anticipated that either the top or bottom electrodes of the FECap may be used as the local interconnection layer for the purpose of interconnecting multiple circuit elements. It is further anticipated that both the top and bottom electrodes may be used as local interconnection layers for interconnecting various combinations of multiple circuit elements and multiple segments of one or more metal layers such as the M1 layer. Circuit elements may include, for example, active regions such as the source, drain or gate of a MOS transistor or other such circuit elements in or on a semiconductor substrate. It should be noted, however, that the use of the term xe2x80x9csubstratexe2x80x9d herein, includes the base semiconductor wafer and any epitaxial layers or other type semiconductor layers formed thereover or associated therewith.
The present invention, therefore, takes advantage of the increased FECap surface area required in the layout to interconnect the FECap to the various circuit elements. In addition, the total overall length of the interconnections is shorter in this interconnection structure and scheme, in part, because the interconnection vias are shorter. Manufacturability is also improved due to a reduced number of vias and interconnects. Further, the layout area or layout complexity is reduced in the present invention, as the FECap surface area is unbroken by the area required for contacts and/or vias between the selected circuit elements and the M1 layer.
The ferroelectric memory device of the instant invention is beneficially adapted to provide an additional interconnection layer (local interconnect layer) between multiple circuit elements. As such, the inventor has realized that when the scheme is applied to memory devices requiring larger numbers of interconnections, more benefits of the invention may be derived. The ferroelectric memory device of the present invention comprises first and second circuit elements associated with the ferroelectric memory device, and a ferroelectric capacitor having a conductive plate residing over a first interlevel dielectric layer (ILD). The plate (e.g., top or bottom electrode) of the FECap extends between the first and second circuit elements, providing a local interconnect layer for electrically coupling the first circuit element to the conductive plate directly through a first via, and electrically coupling a second circuit element to the conductive plate directly through a second via, thereby electrically coupling together the circuit elements of the memory device.
The FECap local interconnect layer may be any form or type of conductive plate material used in the ferroelectric capacitor, where the plate forms an integral part of the electrical coupling path between two or more interconnected circuit elements. The FECap local interconnect layer may be used in numerous exemplary FERAM devices, such as the four transistor two capacitor non-volatile SRAM cell (4T/2C NV SRAM), the non-volatile FECap based reference cell, and any other device which requires that an FECap interconnect with two or more circuit elements. For example, one 4T/2C NV SRAM cell requires that each FECap interconnect with three other circuit elements, such as three active regions of three MOS transistors. In another example, a non-volatile reference cell requires that an FECap interconnect with five other circuit elements, such as five active regions of five MOS transistors.
Another aspect of the present invention provides an FECap comprising a first and second conductive plate, where the plates have about the same capacitive surface shape and surface area in the FECap. Beneficially, this provision provides for a formation method in accordance with the present invention, requiring no additional processing in a ferroelectric memory device, (e.g., masking, etching operations). Still another aspect of the present invention provides the FECap comprising a capacitor under bitline architecture.
Another aspect of the invention provides a memory device for storing data in a semiconductor device, which comprises an SRAM memory cell and ferroelectric cell including first and second coupling transistors, first and second access transistors, first and second bitlines, a wordline, and first and second ferroelectric capacitors and which is adapted to store a binary non-volatile data state.
Still another aspect of the invention provides methods for forming a FECap in a FERAM device, in which a plurality of circuit elements associated with the FERAM device in a semiconductor material are provided and individually coupled to one of a plurality of contacts formed over the circuit elements and through openings in a first ILD layer overlying the plurality of circuit elements. The FECap formation method also comprises forming a bottom electrode layer, a ferroelectric dielectric layer, a top electrode layer, and a hard mask over the first ILD layer and the plurality of contacts associated with the circuit elements, and patterning the hard mask layer extending over the plurality of contacts. The FECap formation method further includes selectively etching the bottom electrode layer, the ferroelectric dielectric layer, and the top electrode layer using the hard mask to define a capacitor stack residing over the first ILD layer, where the stack extends between the plurality of contacts and electrically couples together the plurality of circuit elements of the device through the plurality of contacts.